Systemverilog Assertion Without Using Dist

Caroline Mae

2 min read

·

01-01-2025

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SystemVerilog Assertions (SVAs) are a powerful mechanism for verifying the correctness of hardware designs. While the dist operator is often used for concisely expressing timing constraints, it's not always necessary, and sometimes avoiding it can lead to clearer, more understandable assertions. This post explores how to write effective SVAs without relying on the dist operator.

Understanding the dist Operator

Before diving into alternatives, let's briefly recap what the dist operator does. It essentially checks for the distribution of events within a specified timeframe. It's particularly useful for expressing timing relationships where events might occur at slightly different times but still satisfy a constraint. However, its conciseness can sometimes obscure the underlying logic, making debugging and maintenance more challenging.

Alternatives to dist

Several techniques can replace the dist operator, offering improved readability and maintainability:

1. Using always Blocks and Boolean Variables

For simple timing constraints, an always block combined with Boolean variables can effectively replicate the dist functionality. This approach provides a more explicit representation of the timing relationships involved. For example, consider a scenario where you need to check if event A precedes event B within a certain time window. Instead of using dist, you can use an always block to track the occurrence of events and set flags accordingly.

always @(posedge clk) begin
  if (event_a) a_occurred = 1'b1;
  if (event_b && a_occurred) begin
    if ($time - a_time > #10) $error("Event B occurred too late");
    a_occurred = 1'b0;
  end
end

2. Sequential Assertions with Time-Based Constraints

Sequential assertions provide a structured way to express event ordering and timing relationships. Instead of relying on dist, you can explicitly define the time constraints within the assertion itself using the ## operator (delay operator) or the $past system function. This approach makes the timing conditions more transparent.

property event_order;
  @(posedge clk) event_a ##[1:10] event_b;
endproperty

assert property (event_order);

This assertion explicitly states that event b must occur between 1 and 10 clock cycles after event a.

3. Combining Multiple Assertions

Complex timing constraints often benefit from being broken down into smaller, more manageable assertions. This approach can increase readability and make it easier to isolate and debug specific parts of the verification.

Choosing the Right Approach

The decision of whether or not to use the dist operator should be based on a trade-off between conciseness and clarity. For simple scenarios, alternatives like always blocks or sequential assertions might be preferable for their enhanced readability. However, for complex timing relationships, the dist operator can still offer a more compact and efficient solution, provided it doesn't sacrifice clarity. The key is to choose the approach that best suits the specific needs of the assertion and ensures that the verification intent is clearly communicated. Prioritize maintainability and understandability; well-written assertions are crucial for efficient debugging and long-term project success.